The subject invention generally concerns the field of test and measurement instruments, such as digital oscilloscopes and the like, and in particular concerns a novel architecture for digital test and measurement instruments, such as oscilloscopes, or the like.
Modern digital oscilloscopes are generally referred-to as Digital Storage Oscilloscopes (DSOs) or Digital Phosphor Oscilloscopes (DPOs). In either of these types of oscilloscopes, a main feature of the architecture is the use of an A/D (Analog-to-Digital) converter for converting the analog signal under test to a high speed series of digital samples, a demultiplexer for routing the samples to memory, and a circular acquisition memory array for storing the samples. A system microprocessor is used to read the waveform samples from the acquisition memory, and process them for display.
While these oscilloscopes have worked reasonably well up until now, it is herein recognized that there are disadvantages in such an arrangement. One such disadvantage is that prior acquisition memory design described above tends to be relatively expensive in terms of engineering costs, and is difficult to expand. For example, the demultiplexer (demux) IC must be capable of reducing the high Data Input Rate to a slower Write Rate compatible with the operational limits of current memory chips. Furthermore, the maximum possible memory length is limited by the number of address lines on the demux chip.
A second disadvantage lies in the way that prior oscilloscopes handle the data acquisition. That is, data is written into the data acquisition memory in a circular (over-writing) manner until a trigger is detected. Thereafter, in response to the detection of a post-trigger event, the writing process is halted until an external processor reads the waveform data from the acquisition memory. After the data are read-out, the acquisition memory may once again be armed to receive and react to the next trigger event. Specifically, this disadvantage lies in the fact that there is a very large amount of system software overhead (i.e., processing time) resulting from the reading-out and processing of the waveform samples for display. Depending upon the particular algorithms needed to process the waveform samples, a large amount of xe2x80x9cdead timexe2x80x9d could result during which anomalies in the waveform under test might go undetected.
A third disadvantage of prior art digital oscilloscopes is that the memory length is not readily expandable. Some amount of memory expansion may be provided for, but such memory expansion is limited by the amount of available space for memory ICs on the acquisition board and, as noted above, by the memory addressing capability of the demux ICs. Thus, extensive expansion of acquisition memory is not possible without significant engineering development efforts.
What is needed is a new oscilloscope architecture that would reduce the dead time and increase the probability of detecting such anomalies, and that would be easily expandable in terms of memory length.
A xe2x80x9cStreaming Distributed Oscilloscope architecturexe2x80x9d (SDO) comprises at least one channel including a preamplifier module, a Digitizer Module, and an Acquisition Memory Module. An SDO couples all acquired samples of a waveform being monitored to all of its processing boards. Because multiple processor boards can access all of the sample data, an SDO can perform measurements on substantially all samples of a continuous data stream without dead time. An SDO is readily expandable in terms of memory length by simply adding more memory boards, and can be reconfigured by a user by virtue of its object-oriented architecture. An SDO waveform is defined by a trigger source and an acquisition memory. An SDO is capable of acquiring multiple waveforms based upon different triggers from the same data stream in the same channel. An SDO timebase for a given channel is defined by a decimator followed by an acquisition memory. Multiple timebases can co-exist in the same SDO channel.